DMA controller for UHS

Purpose: 	write blocks of data to ram directly from a 5380 scsi
		controller in sizes up to 65536 bytes

Implementation: The circuit will be implemented in programmable logic,
		preferrably in the form of ISP-friendly ee-logic

Registers:	
 Size	Name		Description
 WORD	uhs_startaddr	Destination address for read/write
 WORD	uhs_numbytes	Number of bytes to transfer
 BYTE	uhs_piodata	PIO data register (read uhs_comctl desc)
 BYTE	uhs_comctl	Command and Control register for the DMAC

uhs_comctl register:
WRITE:
 Bit(s)	Name		Description
 7	uhs_r_w		Read/Write control (relative to computer)
 5-4	uhs_dma_mode	Set DMA mode (0=PIO 1=blocking 2=transient
			3=reserved)
 2 	uhs_irqen	Enable IRQ on end-of-DMA
 1	uhs_addrlck	Clear to auto-increment dest/src addr
 0	uhs_dma_reset	Reset the DMAC (equivalent to !reset being pulled)
READ:
 7	uhs_dma_ok	Set if the DMA operation completed with no problems
 6	uhs_dma_busreq	Set if the scsi bus requests attention before the 
			end of the transfer
 5	uhs_dma_fin	Set when a DMA operation is finished
 2	uhs_dma_irq	Set when an IRQ condition occurs